Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!ucbvax!hplabs!hplabsz!kleinman
From: kleinman@hplabsz.HPL.HP.COM (Bruce Kleinman)
Newsgroups: comp.arch
Subject: SRAM vs. DRAM, 33MHz 386 UNIX-PC
Message-ID: <3934@hplabsz.HPL.HP.COM>
Date: 9 Sep 89 20:18:02 GMT
References: <21936@cup.portal.com> <1082@cernvax.UUCP>
Reply-To: kleinman@hplabs.hp.com (Bruce Kleinman)
Organization: Hewlett-Packard Labs, System Architecture Lab, Palo Alto, CA.
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+-------
| You may be running software that has a very low cache hit rate if you
| are doing CAD work or scientific calculations.  Take this little loop
| for example:
| 
|    SUM = 0.0
|    DO 10 I = 1, 1000000
|      SUM = SUM + VEC(I)
| 10 CONTINUE
| 
| A data cache is *no use at all* for this problem.  You will get a
| cache miss on every data access.  Similarly, copying data from one bit
| of memory to another will be limited by the raw memory speed.
+-------
Unless your d-cache line size is wider than a word, and performs burst refills
from main memory.  The '486, for example, will burst fill the 4-word line if
suitably equipped with nibble-mode DRAMs.  Assuming two wait-states for the
initial access, and zero wait states for the sebsequent three, the result is
0.5 wait-states for your example.  Granted, you're still busting the d-cache,
but you are able to take advantage of nibble-mode DRAMs (which tend to be
about the same price as regualr DRAMs).

Bruce "and why would anyone be running FORTRAN code on a PC :-)" Kleinman