Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: PC vs. mainframe I/O (Re: SCSI on steroids)
Message-ID: <31687@ames.arc.nasa.gov>
Date: 11 Sep 89 15:16:58 GMT
References: <21962@cup.portal.com> <3289@scolex.sco.COM>
Sender: usenet@ames.arc.nasa.gov
Organization: NASA - Ames Research Center
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In article <3289@scolex.sco.COM> seanf@sco.COM (Sean Fagan) writes:
>In article <21962@cup.portal.com> cliffhanger@cup.portal.com (Cliff C Heyer) writes:
>>bandwidth. This comes primarily from the memory 
>>cycle time.
>
>Not really.  It comes from the memory bandwidth, which is a bit different
>(ok, not a whole lot, but a bit).

*If* this were really true, it ought to be cheap to build a mainframe style memory
subsystem.  One I know of has 128 banks and 32 ports.  Each port can do one 
read/write per clock period.  I *wish* it were simple to build micros with this
capability.

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117