Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!purdue!mentor.cc.purdue.edu!pur-ee!hankd
From: hankd@pur-ee.UUCP (Hank Dietz)
Newsgroups: comp.arch
Subject: Re: SRAM vs. DRAM, 33MHz 386 UNIX-PC
Message-ID: <12833@pur-ee.UUCP>
Date: 11 Sep 89 15:08:45 GMT
References: <21936@cup.portal.com> <1082@cernvax.UUCP> <3934@hplabsz.HPL.HP.COM> <1083@cernvax.UUCP>
Reply-To: hankd@pur-ee.UUCP (Hank Dietz)
Organization: Purdue University Engineering Computer Network
Lines: 14

In article <1083@cernvax.UUCP> hjm@cernvax.UUCP (Hubert Matthews) writes:
>In article <3934@hplabsz.HPL.HP.COM> kleinman@hplabs.hp.com (Bruce Kleinman) writes:
>>[...I said that data caches aren't any good for long loops...]
...
>But I can always find some access pattern that makes a data cache
>ineffective.  For instance, if the line size of the cache is N bytes,

Yes for conventional cache management, not really for compiler-driven
cache management (as I've said many times before  ;-).  See:

	Chi-Hung Chi, "Compiler-Driven Cache Management Using A State Level
	Transition Model," PhD dissertation, Purdue University, May 1989.

						-hankd@ecn.purdue.edu