Path: utzoo!utgpu!watmath!watdragon!watcsc!colin
From: colin@watcsc.waterloo.edu (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: SRAM vs. DRAM, 33MHz 386 UNIX-PC
Message-ID: <1989Sep11.091647.7235@watcsc.waterloo.edu>
Date: 11 Sep 89 13:16:44 GMT
References: <21936@cup.portal.com> <7851@cbmvax.UUCP> <27133@proton.mips.COM>
Reply-To: colin@watcsc.UUCP (Colin Plumb)
Organization: University of Waterloo Computer Science Club
Lines: 22

>In article <7851@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:
>> [Separate I & D caches] isn't an advantage as an external cache unless your
>> CPU has external I and D busses.  The only one I know of that does is the
>> Motorola 88100.

In article <27133@proton.mips.COM> wilkes@mips.COM (John Wilkes) writes:
> Doesn't the amd 29000 have external I and D busses?  It's been a long time
> since I looked at that chip...

Yes, it does.  The address bus, however, is shared.  Since the MMU can only
translate one address per cycle, it's no bandwidth loss, and things like
pipelined loads and burst mode reduce the number of addresses required.

The only on-chip cache, the branch target cache, stores 4 instructions at
the destination of a branch to give your i-fetch system time to re-establish
a burst, and the prefetch queue will handle bursts interrupted by page
boundaries.

I rather like it.  Note that a working BTC is a comparatively recent
development. :-)
-- 
	-Colin Plumb