Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!bionet!ames!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!cit-vax!tybalt.caltech.edu!sedwards
From: sedwards@tybalt.caltech.edu (Stephen A. Edwards)
Newsgroups: comp.sys.apple
Subject: Re: Apple 2e doesn't see my 6522's !!
Summary: It's a trick....
Message-ID: <11864@cit-vax.Caltech.Edu>
Date: 9 Sep 89 17:54:00 GMT
References: <8909060935.aa25446@SMOKE.BRL.MIL> <34571@apple.Apple.COM>
Sender: news@cit-vax.Caltech.Edu
Reply-To: sedwards@tybalt.caltech.edu (Stephen A. Edwards)
Organization: California Institute of Technology
Lines: 47

I have built three cards now which connect 6522s to the Apple II bus. A trick
is required to actually get the two buggers to talk. The problem is as follows:

The IOSEL' line (decoding the Cn00 space) becomes valid on the rising edge of
the phase 0 clock. However, the 6522 needs its chip select lines valid shortly
/before/ the rising edge of the clock. (I don't have a data sheet handy with
the exact time. Suffice it to say it is in excess of three gate delays.)

There are about three solutions to this problem:

1) Do the address decoding on-board. The address lines become valid much, much
   earlier than the IOSEL' line. This is a bad idea, however, because it makes
   the card slot dependent, or relies on dipswitches to select it. Ugh. This is
   precisely the sort of thing which will make the hardware incompatible with
   future Apple IIs, as well.

2) Delay the rising edge of the phase 0 clock. This would solve the problem,
   but most garden variety 6522s require a symmetric 1 MHz maximum clock.

3) Delay both edges of the clock. This is the solution that I have seen two
   commercial cards ( the Mockingboard, and a generic 6522 card ) use. A
   circuit conditions the phase 0 clock in the following manner:

                      +5            +5         +5
                       |            |          |
                       > +--|(----+ >          >
                       < |        | <          <
               |\      > |  |\    | >    |\    >
               | \     | |  | \   | |    | \   |
  phase 1   ---|  >O---+-+--|  >O-+-+----|  >O-+-- phase 0 to 6522
               | /          | /          | /
               |/           |/           |/

             1/6 74LS05   1/6 74LS05     1/6 74LS05

This is an /ugly/ trick, but when the capacitor and resistor values are chosen
correctly, it works very well. Note that these are open-collector inverters,
which makes the circuit a little more predictable.

The 6522 card I have now exhibits a strange symptom: (I don't have the
capacitor right yet) When I put it in my IIgs, it works perfectly, AS LONG AS
THE MEMORY EXPANSION CARD IS NOT INSTALLED.

Ah, the joys of digital logic...

-Stephen A. Edwards
sedwards@tybalt.caltech.edu