Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!apple!vsi1!daver!wombat!george
From: george@wombat.UUCP (George Scolaro)
Newsgroups: comp.sys.nsc.32k
Subject: Re: Timing question
Message-ID: <309@wombat.UUCP>
Date: 2 Sep 89 17:06:02 GMT
References: <13223@reed.UUCP> <3878@ditka.UUCP>
Reply-To: george@wombat.UUCP (George Scolaro)
Organization: Assn. for the prevention of Polar Bears and Kangaroos
Lines: 27

In article <3878@ditka.UUCP> kls@ditka.UUCP (Karl Swartz) writes:
>In article <13223@reed.UUCP> bob@reed.UUCP (Bob Ankeney) writes:
>>
>>     A quick question:  Which (if either) is faster in execution:
>
>According to my (ancient) manuals, for a 32032 ...
>
>    movw foo(r1),bar(r1)		; 19 cycles
>    movw foo[r1:b],bar[r1:b]		; 27 cycles

On a 32532 (or 32gx32) reading the 32gx32 data 'sheet' the timing is:

     movw foo(r1),bar(r1)		; 4 cycles (5 x 32032)
     movw foo[r1:b],bar[r1:b]		; 8 cycles (3.5 x 32032)

The 32532 has hardware for the addressing modes but the following
still add to the overall instruction time:

	Memory relative		3 clocks (bit cisc)
	External (yuk)		8 clocks (very cisc)
	Scaled Indexing		2 clocks (little cisc)

Note: the above times are added for source and or destination.
-- 
George Scolaro
george@wombat
(try {pyramid|sun|vsi1|killer} !daver!wombat!george)