Path: utzoo!attcan!uunet!ginosko!usc!ucsd!ucbvax!DGP.TORONTO.EDU!dret
From: dret@DGP.TORONTO.EDU (George Drettakis)
Newsgroups: comp.sys.sgi
Subject: Power Series Arch Description Request
Keywords: Cache, Locks, Scheduling, Threads
Message-ID: <89Sep6.182533edt.4956@jarvis.csri.toronto.edu>
Date: 6 Sep 89 22:25:14 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: University of Toronto, CSRI
Lines: 17

I am interested in getting my hands on a document that will describe
the Power Series parallel architecture. 
I am particularily interested in getting information on how the cache is
organised both physically and from a software point of view, the cache
consistency alg., how the hardware locks are implemented 
(the bus structure etc), how spin locks interact with the unix multi-programming
environment, how the scheduler handles the "light-weight" threads and how they
get assigned to processors and how the virtual address space is managed.
A solid, public domain document (paper/tech report/memo/whatever) would be
more than appreciated.
	Thanks,
-- 
George Drettakis (416) 978 5473        Dynamic Graphics Project	
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