Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!oakhill!eifert
From: eifert@oakhill.UUCP (Jim Eifert)
Newsgroups: comp.arch
Subject: Re: Instruction Restart and I/O
Summary: MC68332 uses instruction restart
Message-ID: <2397@sol.oakhill.UUCP>
Date: 13 Sep 89 18:43:36 GMT
References: <1790@cs-spool.calgary.UUCP> <34591@apple.Apple.COM> <1989Sep10.160537.27060@jarvis.csri.toronto.edu>
Reply-To: eifert@sol.UUCP (Jim Eifert)
Organization: Motorola Inc., Austin, Texas
Lines: 21

The MC68332 uses "instruction restart."  Most instructions are considered
completed when the write is received by the bus controller.  When a fault
occurs, both the PC of the instruction to execute upon restarting and the
"released" write are stacked (in addition to some other information  -- see
the manual).  Because of this: on a move memory to memory, a write which is
faulted will not cause the read to be rerun.  When the process is continued,
the write will be queued up, and the next instruction started (or
restarted).

Some instructions such as move multiple are continued from a midpoint,
though a larger stack frame is not required.

Note the the CPU of the MC68332 is a new design and the "virtual memory"
implementation is not necessarily similiar to any other present or future
products.

For those unfamiliar with the MC68332, see "The MC68332 Microcontroller"
in the August 1989 issue of IEEE Micro.  Or refer to the May and
June issues of Microprocessor Report.

Jim Eifert