Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uakari.primate.wisc.edu!ames!ncar!asuvax!mcdphx!udc!chant!aglew From: aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) Newsgroups: comp.arch Subject: Re: Parity in Internal Data Paths of Processors Message-ID: Date: 12 Sep 89 03:02:45 GMT References: <124311@sun.Eng.Sun.COM> Sender: aglew@urbana.mcd.mot.com Organization: Work: Motorola MCD, Urbana Design Center; School: University of Illinois at Urbana-Champaign Lines: 26 In-reply-to: kum@sccmts.Sun.COM's message of 7 Sep 89 23:44:36 GMT >The major microprocessors (that I know of) available in the market >deal with parity only at the bus interface. Are there large systems >(mainframes, supercomputers) that perform additional parity checks >internally and under what conditions? While working for a minicomputer company, I heard that the major difference between minicomputers and microcomputers was that minis did error detection (and occasionally correction) on major functional data paths, not just the bus, and micros didn't. I believe that many minis have internal parity checks - in particular Gould PN and NPs. See the appropriate technical manuals. Academic ref: In the Proceedings of the 8th Symposium on Computer Arithmetic, 1987, Robertson has a paper on extending parity to check for correct functioning of ALUs, etc. -- eg. parity(sum)=sum(parity). Coincidentally, I am doing a literature survey of computer arithmetic under Robertson - I can ask him for further refs if you want. -- Andy "Krazy" Glew, Motorola MCD, aglew@urbana.mcd.mot.com 1101 E. University, Urbana, IL 61801, USA. {uunet!,}uiucuxc!udc!aglew My opinions are my own; I indicate my company only so that the reader may account for any possible bias I may have towards our products.