Path: utzoo!utgpu!jarvis.csri.toronto.edu!qucis!levisonm
From: levisonm@qucis.queensu.CA (Mark Levison)
Newsgroups: comp.arch
Subject: flexible caches
Keywords: cache registers
Message-ID: <224@qusunr.queensu.CA>
Date: 14 Sep 89 02:46:14 GMT
Organization: Queen's University, Kingston, Ontario, Canada
Lines: 21


   As the caches start to get as smart as we have discussed they
begin to look more and more similar to a peice of fast local
memory or large register set.  A good example of this can be
seen with the Cray-2 which has a 2k (I think maybe more) of very
fast local memory.  The compiler in all of its wisdom makes
decisions about what it wants to store and hopefully does a
better job for vectors and other pathological cases than normal
cache management does.  The only problem with this scheme as I
see it is that the program must know exactly how much local memory
it has in advance (although that might also be a problem for
smart compilers using smart caches) and so programs must be
recompiled for machines with different size local memories.
Does anyone else have any more semi-rational thoughts on this
and where caches might go in the future?

Mark Levison
levisonm@qucis.queensu.ca
Queen's University
Kingston, Ont.
Canada