Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!sun-barr!newstop!sun!imagen!atari!daisy!david
From: david@daisy.UUCP (David Schachter)
Newsgroups: comp.arch
Subject: Re: How Caches Work
Message-ID: <3620@daisy.UUCP>
Date: 14 Sep 89 15:23:32 GMT
References: <21936@cup.portal.com> <1082@cernvax.UUCP> <3985@phri.UUCP> <84g302iO55GB01@amdahl.uts.amdahl.com> <639@unicads.UUCP>
Reply-To: david@daisy.UUCP (David Schachter)
Organization: Daisy/Cadnetix Corp., Mtn. View, CA
Lines: 22


In article <639@unicads.UUCP> les@unicads.UUCP (Les Milash) asks about micro-
computers with a cache line size greater than the memory word size, and wonders
of the absence of such machines.

The Everex Step 386/20 uses a cache line size that depends on the amount of
cache installed.  64KB -> 4 byte line.  128KB -> 8 byte line.  256KB -> 16 byte
line.  The machine is/was the fastest 20 MHz 386 PC clone around.  The Step
386/25 uses the same approach and gets the same results.  Everex calls this
"AMMA", which stands for some marketing drivel.  I don't recall the details on
the Step 386/33.

The cache is a direct-mapped write-back cache, so they clearly brute-forced the
lower hit rate of direct mapping by putting in a lot of cache and devoted
engineering resources that could have gone for multi-way associativity to
write-back logic instead.  In my opinion, they made a good design decision.

The design doesn't use ASICs or custom VLSI; it does use some PALs.

					-- David Schachter

"With friends like you, who needs hallucinations?"  -- "Night Court" (NBC)