Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!voder!tolerant!bruce From: bruce@tolerant.UUCP (Bruce Hochuli) Newsgroups: comp.arch Subject: Re: Parity in Internal Data Paths of Processors Message-ID: <5875@tolerant.UUCP> Date: 14 Sep 89 22:43:31 GMT References: <124311@sun.Eng.Sun.COM> Reply-To: bruce@handel.Tolerant.COM.UUCP (Bruce Hochuli) Organization: Tolerant Software Inc., San Jose CA Lines: 27 In article aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) writes: >>The major microprocessors (that I know of) available in the market >>deal with parity only at the bus interface. Are there large systems >>(mainframes, supercomputers) that perform additional parity checks >>internally and under what conditions? > >While working for a minicomputer company, I heard that the major >difference between minicomputers and microcomputers was that minis did >error detection (and occasionally correction) on major functional data >paths, not just the bus, and micros didn't. I believe that many >minis have internal parity checks - in particular Gould PN and NPs. >See the appropriate technical manuals. > The split that I remember was between mainframes and minicomputers where the mainframes had oodles of error checking and the minis had ECC on the memory, parity on the main bus, and not much more. I was involved in one project where the end product was an IBM 370 clone and the project personnel was about 50/50 mainframe/ minicomputer people. The discussions about internal error checking were very spirited (read screaming, shrieking fights lacking only knives and guns). The minicomputer people won and we did it mini style (just for the record, I was in the losing camp) with minimal error detection.