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From: rod@venera.isi.edu (Rodney Doyle Van Meter III)
Newsgroups: comp.arch
Subject: Re: Filling branch delay slot with test
Message-ID: <9733@venera.isi.edu>
Date: 19 Sep 89 16:31:53 GMT
References: <1432@atanasoff.cs.iastate.edu> <26859@winchester.mips.COM> <1437@atanasoff.cs.iastate.edu> <45219@bbn.COM>
Reply-To: rod@venera.isi.edu.UUCP (Rodney Doyle Van Meter III)
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Organization: Information Sciences Institute, Univ. of So. California
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I came in in the middle of this conversation, but it seems to me that
I was once told that a relatively old machine (early 60s) had a user-
or compiler-settable bit in conditional branch instructions to
indicate which was the more likely path. Keeps your hardware easy,
you only need one prefetch unit, but complicates the life of SW
guys a bit. It's an easy guess in loops; a little harder in IF
statements.

		--Rod