Path: utzoo!attcan!uunet!cs.utexas.edu!rutgers!bpa!cbmvax!snark!eric
From: eric@snark.uu.net (Eric S. Raymond)
Newsgroups: comp.arch
Subject: Re: more soap box
Message-ID: <1StXRx#4TkP4s=eric@snark.uu.net>
Date: 23 Sep 89 07:05:02 GMT
References: <21962@cup.portal.com> <1989Sep12.031453.22947@wolves.uucp>
  <22130@cup.portal.com> <1989Sep16.044013.429@wolves.uucp>
  <259@ssp1.idca.tds.philips.nl> <22308@cup.portal.com> <1SsYy5#6pYhHg=eric@snark.uu.net>
Sender: eric@snark.uu.net (Eric S. Raymond)
Lines: 24

In <1SsYy5#6pYhHg=eric@snark.uu.net> I wrote:
> Part of this is low bus bandwidth (especially on AT-bus machines) but most is
> simply that processor technology has outrun mass-storage technology, very much
> as happened a decade ago when the VAX and other second-generation minis got
> off the ground (the parallel is reinforced by the strong similarity between
> present micro architectures and those minis -- go compare the 680x0
> instruction set to a PDP-11's sometime).

Andrew Klossner pointed out that I used `present' badly here. I was thinking
of standard technology in inexpensive supermicros (386 and 680[123]0 boxes)
rather than the hot new RISC boxes that nobody I know can afford :-). Of
course the 680x0 family is almost ten years old itself now. And minis broke
a bit more than a decade ago. I've *got* to stop posting at 3am in the
morning, dammit... :-) :-)

But I must have said something useful, Andy's note came in hard on the heels of
several thoughtful replies requesting me to expatiate further. Could it
be (gasp) that some comp.arch readers actually feel a need to comprehend
system-balancing and benchmarking issues at *behind the RISCy state of the
art*? The mind reels!

Yet another 3am post from my antediluvian CISC machine...
-- 
      Eric S. Raymond = eric@snark.uu.net    (mad mastermind of TMN-Netnews)