Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!sdsu!crash!pnet01!jca
From: jca@pnet01.cts.com (John C. Archambeau)
Newsgroups: comp.os.minix
Subject: Re: minix on the macintosh
Message-ID: <397@crash.cts.com>
Date: 19 Sep 89 04:16:08 GMT
Sender: root@crash.cts.com
Organization: People-Net [pnet01], El Cajon CA
Lines: 71

dpi@loft386.UUCP (Doug Ingraham) writes:
>Because of a botched design it would be terrible to use the motherboard based
>DMA on the AT.  Here are the reasons.
>
>1)  Transfer rate is poor.  According to the AT Technical Reference Manual
>    Page 1-7 (this is the original 6mhz manual) under system performance.
>    The DMA controller operates at 3 MHz, which results in a clock cycle
>    time of 333 nanoseconds.  All DMA data-transfer bus cycles are five 
>    clock cycles or 1.66 microseconds.  Cycles spent in the transfer of bus
>    control are not included.  If we assume a 512 byte or 256 word transfer
>    the fastest it can go is 425 microseconds.  The CPU will be running at
>    about half speed during this time because of the DMA.
 
For a 6 MHz AT, you are right, but how many of us out there have a 6 MHz AT?
I don't.  I have a 16 MHz 286 box.  Also, the higher speed '286 chips have to
have to have a higher speed support chip set.  Another point, AT bus specs
vary greatly from manufacturer to manufacturer.  IBM didn't set the AT bus
technical specifications in stone, the manual you referred to applies ONLY to
a vintage 6 MHz guinine IBM AT.  A classic offender of varying greatly from
the AT bus spec was Kaypro with their first 10 MHz '286.  The bus ran at 10
MHz along side the CPU...as a result the higher speed cards were born.  The
majority of the '286 motherboards out there are designed to work in an 8 to 10
MHz bus speed (8 being more standard obviously).  Most of my AT cards have a
10 MHz crystal on them.  My motherboard is set up in such a way where I can
run the bus at either full or half CPU clock speed.  It's not set in stone
that such a performance loss would be incurred with a high speed '286
motherboard.  Especially one's with all Harris or AMD chip sets.  Intel is
pretty P'ed at AMD and Harris for cleaning up their mess and making a better
'286.  Won't be too long before the 25 MHz '286's hit the market if they're
not out already.  Such performance losses I'm sure were corrected with the
newer high speed support chip sets.
 
>2)  Transfer for 16 bit operations must go to word boundaries.  See the
>    description under 3 why this is bad.
>
>3)  Transfer must not cross over a 64k memory boundary for 8 bit transfers
>    or 128k boundaries for 16 bit transfers.  Because of limitation 2 and
>    3 the DMA almost always takes place to a buffer on an even byte boundary
>    and guaranteed not to cross a 64k boundary.  This requires the CPU to
>    perform a block move of the data after the DMA operation is complete
>    to put the data in the proper place.  A 256 word move takes an additional
>    172 microseconds at 6 mhz.

I never said that the 80x86 chips weren't brain damaged.  However, in most
cases a pointer will end up being a word or even a paragraph boundary anyway,
so it's not that big of an issue in my opinion.  A smart compiler can adopt
the convention that all pointers are on a word boundary.  The file system
part of the kernel can handle the 64K or 128K DMA problem.  It's just a matter
of dealing with those idiosyncratic annoyances out there that exist in all
machines.  I have yet to see an ideal architecture, everything has its
problems.

>If we are talking about a good implementation of DMA I agree.  Unfortunatly
>on the AT DMA should be used only for the floppy.
 
I do agree that I wouldn't implement DMA on a 6 MHz 286 (if you can find them
anymore).  However, if the later machines can handle it better as I suspect,
then why not use it?  Also, what about DMA on machine equipped with an EISA
bus or MCA?  Would it work better than the classic 6 MHz AT bus?  Most likely,
but then again, how many of us can afford the bus specs for MCA from IBM?

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