Path: utzoo!attcan!utgpu!watmath!att!tut.cis.ohio-state.edu!ucbvax!ucsfcgl!cca.ucsf.edu!root
From: root@cca.ucsf.edu (Systems Staff)
Newsgroups: comp.os.minix
Subject: Re: DMA Discussion
Summary: unforunately ...
Message-ID: <2406@ucsfcca.ucsf.edu>
Date: 21 Sep 89 23:32:04 GMT
References: <24550@louie.udel.EDU>
Organization: Computer Center, UCSF
Lines: 30

In article <24550@louie.udel.EDU>, mcd@ccsitn.att.com writes:
>  
> Actually the discussion about DMA for PC's has been one of the MOST
> informative discussion/thread/topics out of all the myriad things I
> have seen on the list

Yes, too bad some of it is just plain wrong.

For example, some of the discussion compared a single bus cycle of DMA
to a single bus cycle for CPU transfer where the CPU transfer requires
a bus cycle to fetch and another one to store. Although the the clock
count per cycle may be higher, DMA just requires one bus cycle for a
transfer.

Then there is the issue of interrupt handling time blocking other
interrupts.

Etc. etc.

 Thos Sumner       Internet: thos@cca.ucsf.edu
 (The I.G.)        UUCP: ...ucbvax!ucsfcgl!cca.ucsf!thos
                   BITNET:  thos@ucsfcca

 U.S. Mail:  Thos Sumner, Computer Center, Rm U-76, UCSF
             San Francisco, CA 94143-0704 USA

I hear nothing in life is certain but death and taxes -- and they're
working on death.

#include <disclaimer.std>