Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!csd4.csd.uwm.edu!bionet!agate!ucbvax!POSTGRES.BERKELEY.EDU!dillon
From: dillon@POSTGRES.BERKELEY.EDU (Matt Dillon)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Amiga 3000 rumors
Message-ID: <8909160120.AA05128@postgres.Berkeley.EDU>
Date: 16 Sep 89 01:20:26 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Lines: 20

:>I do think that the A3000 REALLY should have a scalable-speed asynchronous
:>design.  By that, I mean that the user, by replacing the CPU and some other
:>(socketed) chips, should be able to upgrade their 25Mhz A3000 to a 33 Mhz
:>A3000 (unless you want to ship it as a 33Mhz machine ...).  They should also
:>be able to upgrade it to a 50Mhz machine, and so on, when the CPU is available
:
:Well, the only hard part is that the 50 Mhz version is probably going
:to require a controlled impedance PC board (ie multiwire) and fully
:terminated nets, which will cause the size, complexity, and expense
:of the design to mushroom.  Most likely a 50 Mhz uP chip would have
:to run asynchronously on a daughter card in the 3000, unless they are
:planning on pricing it out of reach of most of us.

	If a large cache, say 16K+, were integral to the design (i.e.
    the processor clock is restricted to the motherboard) you could
    run the processor at 50 MHz through a high speed cache and run the
    main bus at something more reasonable (10+ MHz), and still get great
    performance out of the thing.

						-Matt