Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!ginosko!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Humor me
Message-ID: <378@crdos1.crd.ge.COM>
Date: 18 Sep 89 19:09:42 GMT
References: <19568@gryphon.COM> <293@crdos1.crd.ge.COM> <1214@marlin.NOSC.MIL> <701@philmtl.philips.ca>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: GE Corp R&D Center
Lines: 22

In article <701@philmtl.philips.ca>, ray@philmtl.philips.ca (Raymond Dunn) writes:
|  In article <307@crdos1.crd.ge.COM> davidsen@crdos1.UUCP (bill davidsen) writes:
|  >DIPs are 1 bit wide, so for a........
|  
|  In article <14155@netnews.upenn.edu> silver@eniac.seas.upenn.edu.UUCP (Andy Silverman) responds:
|  >Correct me if I'm wrong, but the number of bits wide a given chip is entirely
|  >up to the chip designers....

  You're obviously correct, but if a vendor wants to sell a chip, it had
better either be what the market expects or something very much better.
In the case of DIPs, the standard has been 1 bit for large sizes, with
some items also available in 4 bit. I often wondered if there would be a
markey for a four byte wide chip with ECC on the chip, and two status
pins coming out for "soft error" and "hard error." Because of the way
most ECC works, it is cheaper to do ECC on more bits wide, since schemes
like Hamming take log2N+1 bits for the correction data (6 bits of ECC
data for 32 bits of "normal" data).
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon