Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!orstcs!prism!johng
From: johng@prism.cs.orst.edu (John A. Gregor)
Newsgroups: comp.arch
Subject: Re: Asynchronous cpu
Keywords: Asynchronous logic design
Message-ID: <12892@orstcs.CS.ORST.EDU>
Date: 5 Oct 89 09:22:47 GMT
References: <5241@dime.cs.umass.edu>
Sender: usenet@orstcs.CS.ORST.EDU
Reply-To: johng@cloud.ATS.ORST.EDU (John A. Gregor)
Organization: Oregon State Univ. -- Computer Science
Lines: 20

In article <5241@dime.cs.umass.edu> yodaiken@freal.cs.umass.edu (victor yodaiken) writes:
>In the June 89 SIGARCH there's an article by Martin, Burns and a couple
>of other folks from CALTECH on using the self-timed (asynchronous) 
>circuits that they've been pushing at CALTECH to build a processor. 

Perfect timing!

For my EE 478 (Computer Architecture) class we have to do a report and
a presentation.  I'm looking at doing mine on asynchronous logic
design.  Does anyone out there have some good references?  Any personal
experiences, observations, warnings, anecdotes, etc. you wish to
share?  Also, what I really need are some pointers to actual machines
or subsystems that have been implemented in asynchronous logic.

All information will be greatly appreciated.  I'll summarize what I get
if there is interest.

John Gregor                           423 Cauthorn Hall
johng@cloud.ATS.ORST.EDU              Oregon State University
(503) 737-8426                        Corvallis, OR  97331