Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!texbell!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.arch Subject: Re: (Im)precise exceptions Message-ID: <6429@ficc.uu.net> Date: 5 Oct 89 15:04:58 GMT References: <2353@oakhill.UUCP> <261500010@S34.Prime.COM> <34701@apple.Apple.COM> <1989Oct5.031321.2115@esegue.segue.boston.ma.us> Organization: Xenix Support, FICC Lines: 14 Followups-to: comp.misc A philosophical digression: Why do I get the feeling that a RISC program counter is kind of a fuzzy heisenbergian particle? It's as if RISC has run into a sort of digital equivalent of quantum indeterminacy. You can know the exact state of your CPU, or you can run fast, but you can't do the two at once. (Apologies if you think this is rather a shallow idea, I don't deal much with RISCs in the Real World.) -- Peter da Silva, *NIX support guy @ Ferranti International Controls Corporation. Biz: peter@ficc.uu.net, +1 713 274 5180. Fun: peter@sugar.hackercorp.com. `-_-' ``I feel that any [environment] with users in it is "adverse".'' 'U` -- Eric Peterson