Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!apple!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: (Im)precise exceptions
Message-ID: <28842@winchester.mips.COM>
Date: 6 Oct 89 00:21:29 GMT
References: <2353@oakhill.UUCP> <261500010@S34.Prime.COM> <34701@apple.Apple.COM> <1989Oct5.031321.2115@esegue.segue.boston.ma.us> <6429@ficc.uu.net>
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
Lines: 23

In article <6429@ficc.uu.net> peter@ficc.uu.net (Peter da Silva) writes:
>A philosophical digression:
>
>Why do I get the feeling that a RISC program counter is kind of a fuzzy
>heisenbergian particle? It's as if RISC has run into a sort of digital
>equivalent of quantum indeterminacy. You can know the exact state of your
>CPU, or you can run fast, but you can't do the two at once.
>
>(Apologies if you think this is rather a shallow idea, I don't deal much
>with RISCs in the Real World.)

The Heisenberg analogy is not bad.  However, it has nothing to do
with whether something is RISC or not.  It's much more likely to
be related to a machine that is a) heavily pipelined, and especially if
it b) does true out-of-order execution.  Neither of these are exclusive
to RISCs.  Of course, typical RISC designs may make it easier to
use deeper pipelining with less complexity of undoing/shadowing, etc.

-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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