Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!wugate!uunet!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: (Im)precise exceptions
Message-ID: <8123@cbmvax.UUCP>
Date: 7 Oct 89 02:09:32 GMT
References: <2353@oakhill.UUCP> <261500010@S34.Prime.COM> <34701@apple.Apple.COM> <1989Oct5.031321.2115@esegue.segue.boston.ma.us> <6429@ficc.uu.net> <28842@winchester.mips.COM>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 19

In article <28842@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>In article <6429@ficc.uu.net> peter@ficc.uu.net (Peter da Silva) writes:
>>A philosophical digression:
...
>The Heisenberg analogy is not bad.  However, it has nothing to do
>with whether something is RISC or not.  It's much more likely to
>be related to a machine that is a) heavily pipelined, and especially if
>it b) does true out-of-order execution.  Neither of these are exclusive
>to RISCs.  Of course, typical RISC designs may make it easier to
>use deeper pipelining with less complexity of undoing/shadowing, etc.

	The RPM-40 has an interesting trick to avoid problems like this:
it keeps a "queue" of PC values (and a few other internal values).  This
makes restart easy (and it only takes 8 cycles to store all the queues).

-- 
Randell Jesup, Keeper of AmigaDos, Commodore Engineering.
{uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com  BIX: rjesup  
Common phrase heard at Amiga Devcon '89: "It's in there!"