Xref: utzoo comp.arch:11694 comp.sys.ibm.pc.rt:1035 Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!gem.mps.ohio-state.edu!usc!bloom-beacon!eru!luth!sunic!mcsun!tuvie!edvvie!eliza!johnny From: johnny@edvvie.at (Johann Schweigl) Newsgroups: comp.arch,comp.sys.ibm.pc.rt Subject: Result of RT integer alignment problem / other CPU's Keywords: CPU RT ROMP alignment Message-ID: <170@eliza.edvvie.at> Date: 6 Oct 89 05:16:31 GMT Organization: Edv GesmbH, Austria/Europa Lines: 38 Got a lot of reactions on this topic, so I decided to post a summary of other CPU's behaviour to the net. Thanks to everyone who provided this information. CPU Action on unaligned access --------------------------------------------------------------------------- IBM ROMP(032) strips the two LSB's off the address, writes to the so word aligned address SPARC trap, 2,4 and 8-byte alignment for corresponding types MIPS trap, 2 and 4-byte alignment for corresponding types extra instructions for unaligned load/stores AM29000 selectable through Unaligned Access Trap Enable bit. If set, a trap occurs and information about the event is placed in some special registers. Trap handler may abort or set other actions. If not set, address will be aligned 88000 trap HP Spectrum(PA) trap, extra instruction for unaligned store GE600/6000, Honeywell DPS strips LSB, aligning on 2-byte boundaries 68000, 68010 require 2-byte alignment on 2-byte data, trap if not. combinations of trap and not trap on 4-byte data 68020, 68030 write to unaligned address, need extra fetches 80386, 80486 write to unaligned address, need extra fetches VaxStation 2000 write to unaligned address, no info about fetches IBM /360 trap IBM /370, later write to unaligned address, no info about fetches Bye, johnny -- This does not reflect the | Johann Schweigl | DOS machines? opinions of my employer. | johnny@edvvie.at | I don't hate DOS machines. I am busy enough by talking | | I just feel better when I about my own ... | EDVG Vienna | don't see one ...