Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!ico!vail!rcd
From: rcd@ico.ISC.COM (Dick Dunn)
Newsgroups: comp.arch
Subject: ERISC???
Message-ID: <16190@vail.ICO.ISC.COM>
Date: 11 Oct 89 06:43:02 GMT
Organization: Interactive Systems Corp, Boulder, CO
Lines: 21

This week's EE Times features a front-page article about IBM's forthcoming
line of RISC machines based on the `America' processor, presented at ICCD.
The article mentions that the architecture has 184 instructions!

I don't know whether the EE Times folks got the count wrong (by somehow
double-counting for addressing modes or some such) or don't know what RISC
stands for...but it's clearly time for a new acronym:
	ERISC - Extended Reduced Instruction Set Computer
as in "our machine has more fewer instructions than yours doesn't."

It would be interesting to know what the machine really looks like.  Of
course, EE Times doesn't give any information about speed, and only one
vague guess about cost.  The machine won't be out until some time next
year.  But that doesn't stop them from proclaiming that IBM is at the head
of the pack!  It's interesting that you can take the lead by talking about
what you're going to do...this wasn't even a product (pre)announcement.

Sigh...this sort of non-journalism doesn't do anyone--even IBM--any good.
-- 
Dick Dunn     rcd@ico.isc.com    uucp: {ncar,nbires}!ico!rcd     (303)449-2870
   ...No DOS.  UNIX.