Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!cica!gatech!eedsp!lagrange!aaronb
From: aaronb@lagrange.gatech.edu (Aaron Birenboim)
Newsgroups: comp.arch
Subject: Re: Self-modifying code
Message-ID: <527@eedsp.gatech.edu>
Date: 12 Oct 89 14:11:32 GMT
References: <1080@mipos3.intel.com> <1989Oct11.013553.3893@esegue.segue.boston.ma.us>
Reply-To: aaronb@lagrange.UUCP (Aaron Birenboim)
Organization: Georgia Institute of Technology
Lines: 19

In article <1989Oct11.013553.3893@esegue.segue.boston.ma.us> johnl@esegue.segue.boston.ma.us (John R. Levine) writes:

>...  Most computers fetch
>instructions considerably ahead of where they are executing; even the lowly
>8086 can fetch up to 6 bytes ahead of where it is executing.  This means that
>if you store into the next instruction, the CPU might or might not already
>have fetched that instruction, so it might execute the old instruction or the
>new one, depending on such things as interrupts, DMA, and even register
>contents.  Needless to say, this kind of bug is very hard to find.

Is this really true?  There isn't enough dependancy checking in the
8086 instruction pipe to detect this type of operation, clear
the pipe, and re-fetch the altered instruction, or some such
corrective measure.  I'm glad I don't try self-modifying code.

Aaron Birenboim        | aaronb@eedsp.gatech.edu |  Why do we have to wear
Georgia Tech Box 30735 | (404) 874-1973          |  shoes all the time?
Atlanta, GA 30332      +-------------------------+  
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