Xref: utzoo comp.sys.dec:1922 comp.sys.dec.micro:808
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!gem.mps.ohio-state.edu!ginosko!uunet!munnari.oz.au!murtoa.cs.mu.oz.au!gwydir!gara!dheap
From: dheap@gara.une.oz (Dave Heap PSYS)
Newsgroups: comp.sys.dec,comp.sys.dec.micro
Subject: Re: PDP-11 and LSI-11 Opcodes
Message-ID: <1201@gara.une.oz>
Date: 10 Oct 89 01:38:10 GMT
References: <1989Sep11.221225.17780@cs.rochester.edu>
Reply-To: dheap@gara.UUCP (Dave Heap PSYS)
Organization: Uni. of New England, Armidale, NSW.
Lines: 21

In article <1989Sep11.221225.17780@cs.rochester.edu> yamauchi@cs.rochester.edu.UUCP (Brian Yamauchi) writes:
>Do the PDP-11 and the LSI-11 have the same instruction set and use the
>same opcodes?
>
	Basically, yes. All PDP11s (including the LSI11) support the basic
PDP11 instruction set. A few exceptions such as SOB, MARK, RTT & SXT are not
supported on all. Optional instructions such as EIS & floating point depend
on the CPU &/or its fitted options. Minimal differences exist between CPUs
for unusual instructions such as MOV R1,(R1)+ where autoincrementing may take
place before or after R1 is read, depending on the processor. In general,
you shouldn't have any problems. If you really need it, I have documentation
of PDP11 family differences.

	(Sorry about the late reply, I mailed this direct, went on holiday
& returned to find it had bounced.)

-- 
Dave Heap              	         ACSNET: dheap@gara.une.oz                  
Psychology Department,           UUCP: ...!uunet!munnari!gara.une.oz!dheap  
University of New England,       ARPA: dheap%gara.une.oz@uunet.uu.net       
Armidale NSW 2351, Australia