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From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Self-modifying code
Message-ID: <33557@ames.arc.nasa.gov>
Date: 13 Oct 89 19:02:15 GMT
References: <6481@pt.cs.cmu.edu> <9175@etana.tut.fi> <1619@atanasoff.cs.iastate.edu> <855@sdrc.UUCP>
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Some of this discussion reminds me of discussions about threaded-code systems
like Forth.  Has anyone ever identified any ISA issues that are specific for
code like this?  I have always assumed that a fast branching RISC would be
ideal, but I don't know of this is a correct assumption.
(I am not asking for a repeat of RISC arguments: any instruction, to be
considered, has to show at least a 1% speedup on an actual complete program
to be considered for special support.)

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117