Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!oliveb!amdahl!dgcad!gary
From: gary@dgcad.SV.DG.COM (Gary Bridgewater)
Newsgroups: comp.arch
Subject: Re: Self-modifying code
Message-ID: <1172@svx.SV.DG.COM>
Date: 14 Oct 89 07:47:24 GMT
References: <6481@pt.cs.cmu.edu> <9175@etana.tut.fi> <16557@siemens.siemens.com>
Reply-To: gary@svx.SV.DG.COM ()
Organization: Data General SDD, Sunnyvale, CA
Lines: 34

In article <16557@siemens.siemens.com> fwb@demon.UUCP (Frederic W. Brehm) writes:
>In article <9175@etana.tut.fi> pl@etana.tut.fi (Lehtinen Pertti) writes:
 >>	I've been lately wondering if there is any architecture
 >>	with possibility to execute instruction indirectly.
 >>...
 >>	I mean something like:
 >>
 >>		exec r0	; execute instructio in register r0
 >>...
 >>	Does anyone know?
 >
 >The Data General Eclipse (16-bit) had an instruction just like this.  I
 >don't know if the MV series has one like it.

 The MV instruction set includes the Eclipse instruction set which includes
 the Nova instruction set. Assembly routines writtern for the first Nova
 run on the latest MV.
 The most useful purpose, on our I/O architecture, for the XCT instruction
 is to write self-modifying re-entrant I/O handlers:
	load accumulator 0 with an I/O instruction  with a 0 device code
	OR in the device code of interest
	XCT accumulator 0 
So you have one generic disk handler for each type of disk which can handle
any number of controllers.
You can also write a fairly tight loop via
	load accumulator 0 with an XCT 0
	XCT 0
which was kind of an interesting thing to watch back when we had lights - the
u-code address lights came on fairly solid and the address lights froze. This
can be interrupted but the cpu can't be halted since halt is only honored 
between instructions.
-- 
Gary Bridgewater, Data General Corp., Sunnyvale Ca.
gary@sv4.ceo.sv.dg.com or 
{amdahl,aeras,amdcad,mas1,matra3}!dgcad.SV.DG.COM!gary
No good deed goes unpunished.