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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Re: test and set facility
Keywords: MIPS
Message-ID: <29463@obiwan.mips.COM>
Date: 14 Oct 89 13:58:30 GMT
References: <200@rangkom.MY>
Lines: 42

In article <200@rangkom.MY> napi@rangkom.MY (Mohd Hanafiah b. Abdullah) writes:
>I may have missed the obvious, but how would one implement
>semaphore type operations on a MIPS machine as I have not
>noticed any "test and set" instruction available. External hardware
>perhaps?
>


   $ From: jeffd@norge.sgi.com (Jeff Doughty)
   $ Newsgroups: comp.sys.mips
   $ Subject: Re: atomic instructions on R2000
   $ Message-ID: <769@odin.SGI.COM>
   $ Date: 3 Oct 89 15:24:39 GMT

   $ > This may be a naive question, but...
   $ 
   $ > In Kane's MIPS R2000 book, I can't find any reference to 
   $ > atomic instructions, like swap or test-and-set.  Are there
   $ > really none, or am I missing something?  If not, how do
   $ > MIPS-based multiprocessors implement locks?
   $ 
   $ 
   $ It is not naive at all.  The SGI PowerSeries machines, which use
   $ multiple R2000's and R3000's implement test-and-set spinlocks with
   $ a custom gate-array per processor and a private bus.  The gate-array
   $ is actually a bus-watching cache that maintains the state of 64K
   $ spinlocks.  We kernel guys grab 32K and allow the users 32K.  They
   $ are mapped into a process's address space and accessed like memory.
   $ 
   $ Moving the synchronization traffic to a separate bus has several
   $ advantages - the primary reason being that it takes load off the
   $ memory bus.  In addition, we can taylor the latency requirements
   $ and cache coherency protocols to lock traffic, rather than having
   $ one bus design that does everything non-optimally).
   $ 
   $ 				Jeff Doughty
   $ 				IRIX group
   $ 				Silicon Graphics, Inc.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}