Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!gem.mps.ohio-state.edu!uakari.primate.wisc.edu!nic.MR.NET!thor.acc.stolaf.edu!mike
From: mike@thor.acc.stolaf.edu (Mike Haertel)
Newsgroups: comp.arch
Subject: Re: ATTACK OF KILLER MICROS
Message-ID: <7369@thor.acc.stolaf.edu>
Date: 15 Oct 89 19:24:01 GMT
References: <35825@lll-winken.LLNL.GOV> <1081@m3.mfci.UUCP>
Reply-To: mike@thor.stolaf.edu ()
Organization: St. Olaf College, Northfield, MN
Lines: 16

In article <1081@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes:
>I take my hat off to them, too, because that's no mean feat.  But don't
>forget that the supercomputers didn't set out to be the fastest machines
>on scalar code.  If they had, they'd all have data caches, non-interleaved
>main memory, and no vector facilities.  What the supercomputer designers

Excuse me, non-interleaved main memory?  I've always assumed that
interleaved memory could help scalar code too.  After all, instruction
fetch tends to take place from successive addresses.  Of course if
main memory is very fast there is no point to interleaving it, but
if all you've got is drams with slow cycle times, I would expect
that interleaving them would benefit even straight scalar code.
-- 
Mike Haertel <mike@stolaf.edu>
``There's nothing remarkable about it.  All one has to do is hit the right
  keys at the right time and the instrument plays itself.'' -- J. S. Bach