Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!asuvax!mcdphx!udc!chant!aglew From: aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) Newsgroups: comp.arch Subject: Re: Self-modifying code Message-ID: Date: 13 Oct 89 12:33:28 GMT References: <1080@mipos3.intel.com> <1989Oct11.013553.3893@esegue.segue.boston.ma.us> Sender: aglew@urbana.mcd.mot.com Organization: Work: Motorola MCD, Urbana Design Center; School: University of Illinois at Urbana-Champaign Lines: 21 In-reply-to: johnl@esegue.segue.boston.ma.us's message of 11 Oct 89 01:35:53 GMT You might consider instructions of the form "Execute Register" or "Execute Memory", where the primary instruction specified where a (single) second instruction was to be fetched from, a form of self-modifying code. Certainly, these caused the same difficulties for the pipeline. I have seen "Execute Register" used to synthesize dynamic shift instructions, where the shift amount is not known at compile time (dynamic shifts are much less frequent than static shifts in most instruction mixes), and to produce the indirect syscall() system call. "Execute Register" was also used to produce a relatively fast instruction level simulator for a similar, but not identical, instruction set processor. -- Andy "Krazy" Glew, Motorola MCD, aglew@urbana.mcd.mot.com 1101 E. University, Urbana, IL 61801, USA. {uunet!,}uiucuxc!udc!aglew My opinions are my own; I indicate my company only so that the reader may account for any possible bias I may have towards our products.