Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!lll-winken!vette!brooks
From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: ATTACK OF KILLER MICROS
Message-ID: <35977@lll-winken.LLNL.GOV>
Date: 17 Oct 89 01:02:25 GMT
References: <35825@lll-winken.LLNL.GOV> <1081@m3.mfci.UUCP> <35896@lll-winken.LLNL.GOV> <33798@ames.arc.nasa.gov>
Sender: usenet@lll-winken.LLNL.GOV
Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
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In article <33798@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
>>Supercomputers of the future will be scalable multiprocessors made of many
>>hundreds to thousands of commodity microprocessors.
>
>The appropriate interconnection technology for this has not, to my knowledge,
>been determined.  Perhaps you might explain how it will be done?  The rest,
>I agree, is doable at this point, though some of it is not trivial.
This is the stuff of research papers right now, and rapid progress is being
made in this area.  The key issue is not having the components which establish
the interconnect cost much more than the microprocessors, their off chip caches,
and their main memory.  We have been through message passing hypercubes and
the like, which minimize hardware cost while maximizing programmer effort.
I currently lean to scalable coherent cache systems which minimize programmer
effort.  The exact protocols and hardware implementation which work best
for real applications is a current research topic. The complexity of the
situtation is much too high for a vendor to just pick a protocol and build
without first running very detailed simulations of the system on real programs.


brooks@maddog.llnl.gov, brooks@maddog.uucp