Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uwm.edu!uwvax!rang From: rang@cs.wisc.edu (Anton Rang) Newsgroups: comp.arch Subject: Re: parallel systems vs. uni-processors Message-ID: Date: 17 Oct 89 23:15:46 GMT References: <35825@lll-winken.LLNL.GOV> <20336@princeton.Princeton.EDU> <308@argosy.UUCP> Sender: news@spool.cs.wisc.edu Organization: UW-Madison CS department Lines: 30 In-reply-to: ian@argosy.UUCP's message of 17 Oct 89 20:39:54 GMT In article <308@argosy.UUCP> ian@argosy.UUCP (Ian L. Kaplan) writes: >In article <20336@princeton.Princeton.EDU> mg@notecnirp.edu (Michael Golan) writes: >>2) A lot of research is going on - and went on for over 10 years now. As far >>as I know, no *really* scalable parallel architecture with shared >>memory exists that will scale far above 10 processors (i.e. 100). And >>it does not seems to me this will be possible in the near future. > > By this narrow deffinition, the statement is more or less correct. >Classic shared memory MIMD systems with snoopy caches saturate >rapidly. However, this is simply the wrong approach to the problem. >SIMD architectures like the Connection Machine are scalable. Perhaps >you did not study these. The group working on the IEEE SCI (scalable coherent interconnect) claims that they will be able to handle up to 65,536 processors in either a message-passing or shared-memory environment. I haven't had a chance to read all their working papers, but it does seem that their stuff should scale well to 100-500 processors, at least. Their goal is 1 GB/sec bandwidth per processor (16 bits every 2 ns), and the interface chips are supposed to be available next year. (I'm eagerly waiting to see what this looks like... :-) The reference number for the standard is IEEE P1596.... Anton +----------------------------------+------------------+ | Anton Rang (grad student) | rang@cs.wisc.edu | | University of Wisconsin--Madison | | +----------------------------------+------------------+