Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!wugate!uunet!pyrdc!gmu90x!rmiller
From: rmiller@gmu90x.UUCP (Richard Miller)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <2398@gmu90x.UUCP>
Date: 19 Oct 89 03:38:32 GMT
References: <16190@vail.ICO.ISC.COM> <2393@gmu90x.UUCP> <1087@m3.mfci.UUCP>
Reply-To: rmiller@gmu90x.UUCP (Richard Miller)
Organization: George Mason University, Fairfax, Va.
Lines: 61

With reference to the IBM America processor, in article <2393@gmu90x.UUCP>
rmiller@gmu90x.UUCP I wrote:
>>I believe that the only reason that the term RISC is associated with this
>>architecture is for the marketing mileage that it gives them.  Perhaps
>>their efforts to redefine term are a token effort to assuage the confusion
>>of those that can see through this somewhat blatant marketing ploy.

In article <1087@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes:
>It might help to consider a few more facts associated with this machine.
>The first is that the guy who started the whole RISC juggernaut was John
>Cocke, who was (and is) at IBM, and who was also involved (at least initially)
>with this America processor.  The second is that the papers on the IBM 801
>which enunciated the principles embodied therein don't emphasize the same
>things that the research efforts at Berkeley & Stanford did, so it's not
>that surprising that they don't religiously follow the tenets espoused
>by them...

It is interesting to note that Radin, in the earliest publication that I
have on the 801 [The 801 Minicomputer, George Radin, IBM Journal of Research
and Development, 27(3), May 1983] starts off his paper by stating that the
distinguishing feature of the architecture is that it has a "straightforward,
rather primitive machine cycle" and that "A similar general approach has
been pursued by a group at the University of California."  It is also
interesting that the term RISC is never used in the article, even though
the term had already been published (in an article referenced by Radin!).

You do have a good point in that Radin emphasizes a clean pipeline cycle
more than hardware minimization -- but it's hard to believe that the register
renaming in the FPU is "free" by either metric.

>
>On the other hand, you could have a point.  It just seems kinda weird to
>accuse the guys who started all this of mere marketing ploys.  

The basic question that I have is:

Why would IBM not refer to the 801 as a RISC in an article published 6
years ago and call the America (which, by almost every metric ever
seriously considered is less RISCy) a RISC at its initial announcement?
I can't think of any reason other than marketing hype.

>Besides,
>if the machine is as fast as they say, and if it doesn't qualify as a RISC
>(under some hypothetical reasonable definition of RISC), then it would
>seem some interesting (and undoubtedly amazingly inflammatory) conclusions
>might present themselves...
>
Please don't interpret what I said as a knock of the design! After talking to a
couple of presenters at ICCD, I was very impressed by both their design and
their design philosophy.  It's (going to be) a great chip.  I just wish they
had called the 801 a RISC and left it out (or at least not blared it) in the
America -- why blow smoke on a foggy day! ;)  I have a feeling that the RISC
"conclusions" that you imply have already been reached by many design teams.

Rick Miller
11012 Howland Drive
Reston, VA  22091

The opinions expressed here are my own.

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