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From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <1261@crdos1.crd.ge.COM>
Date: 19 Oct 89 12:51:42 GMT
References: <16190@vail.ICO.ISC.COM> <2393@gmu90x.UUCP> <1087@m3.mfci.UUCP> <1989Oct19.044615.7973@ico.isc.com>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: GE Corp R&D Center
Lines: 20

In article <1989Oct19.044615.7973@ico.isc.com>, rcd@ico.isc.com (Dick Dunn) writes:
|  Nor am I, but that wasn't the point.  The America processor, if you believe
|  the _EE_Times_ article that started this (a notable "if"!), has substan-
|  tially more instructions than, say, an 80386.  It may be fast, but that's
|  not a reduced instruction set.  If they've made a new fast computer, let's
|  call it a new fast computer and not slap the "RISC" label on it just
|  because RISC is in vogue.

  Yes. I guess that one feature which separates (usually) RISC and CISC
is hardwired vs. microcoded instructions. The America processor may be a
RISC by that standard, I don't have enough info to guess. Then what do
you call a CPU like the 486 or 68040 which seem to have a mix of
hardcoded common instructions and microcode for instruction set
richness? It was easier to identify the players when the characteristics
were vastly diferent.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
"The world is filled with fools. They blindly follow their so-called
'reason' in the face of the church and common sense. Any fool can see
that the world is flat!" - anon