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From: hsu@uicsrd.csrd.uiuc.edu (William Tsun-Yuk Hsu)
Newsgroups: comp.arch
Subject: Re: ATTACK OF KILLER MICROS
Message-ID: <1989Oct19.172050.20818@ux1.cso.uiuc.edu>
Date: 19 Oct 89 17:20:50 GMT
References: <35825@lll-winken.LLNL.GOV> <1081@m3.mfci.UUCP> <35896@lll-winken.LLNL.GOV> <33798@ames.arc.nasa.gov> <35977@lll-winken.LLNL.GOV> <220@dg.dg.com>
Sender: news@ux1.cso.uiuc.edu (News)
Reply-To: hsu@uicsrd.csrd.uiuc.edu (William Tsun-Yuk Hsu)
Organization: Center for Supercomputing Research and Development, Univ. of Illinois
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In article <220@dg.dg.com> chris@dg.dg.com (Chris Moriondo) writes:
>
>The only really scalable interconnect schemes of which I am aware are
>multistage interconnects which grow (N log N) as you linearly increase the
>numbers of processors and memories...
>
>While message passing multicomputers maximize programmer effort in the sense
>that they don't lend themselves to "dusty deck" programs, they have the
>advantage that the interconnect costs scale linearly with the size machine.

Ummm, message passing does not necessarily mean a single-stage 
interconnect. Also, most commercial message passing systems these
days are hypercubes, and it's oversimplifying to claim that the
cost of the hypercube interconnect scales linearly with system size.
Remember that there are O(logN) ports per processor. Check out the
paper by Abraham and Padmanabhan in the '86 International Conference
on Parallel Processing, for another view on interconnect cost
and performance comparisons.

Most point-to-point parallel architectures, where the fan-out per
processor also grows linearly with the system size, tend to be
things like rings and meshes that are less popular for more
general purpose parallel computing. Are you referring to these
rather than hypercubes?

Bill Hsu