Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!uwm.edu!lll-winken!vette!brooks
From: brooks@vette.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: ATTACK OF KILLER MICROS
Message-ID: <36281@lll-winken.LLNL.GOV>
Date: 20 Oct 89 02:37:07 GMT
References: <35825@lll-winken.LLNL.GOV> <1081@m3.mfci.UUCP> <35896@lll-winken.LLNL.GOV> <33798@ames.arc.nasa.gov> <35977@lll-winken.LLNL.GOV> <220@dg.dg.com> <36249@lll-winken.LLNL.GOV>
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Reply-To: brooks@maddog.llnl.gov (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
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>Assuming 8x8 nodes, a 512 node system takes three stages, a 4096 node
>system takes 4 stages.  Are 4 switch chips cheaper, or equivalent in
>cost to a killer micro and 32 meg of memory?
Oops!  It should be, are 4 switch chips cheaper than 8 killer micros and
256 Meg of memory.  The switch is 4 stages deep, but there are 8 micros
hung on each switch port.  The bottom line is that the switch is probably
not more than half the cost of the machine, even given the fact that it
is not a commodity part.  Of course, a good design for the switch chip
and node interface might become a commodity part!  Depending on the cache
hit rates one might hang more than one micro on each node and further
amortize the cost of the switch.


brooks@maddog.llnl.gov, brooks@maddog.uucp