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From: geraldp@mentor.com (Gerald Page)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <1989Oct19.155752.13028@mentor.com>
Date: 19 Oct 89 15:57:52 GMT
Distribution: usa
Organization: engr
Lines: 32




According to the text "Computer Architecture, a Modern Synthesis", 
by Subrata Dasgupta, John Wiley & Sons, 1989, most RISC processors have
the following 6 characteristics:

1.  All instructions (operations) are register-register type with the exceptions
    of LOAD and STORE, which access main memory.

2.  All instructions (operations) consume a single processor cycle with the
    possible exceptions of LOAD and STORE.

3.  Fixed length, and simple, fixed format instructions that do not cross main
    memory word boundaries.

4.  Relatively few operations and addressing modes. <<<key words "relatively few"

5.  The use of hardwired rather than microcoded control.

6.  The use of instruction pipelining and the concomitant use of compilation
    and delayed branch techniques... to eliminate pipeline distruption due to
    branches.

As has been stated before on the net, RISC was developed for speed.  Reducing
the instruction set is *one* of the ways that RISC achieves that goal.

According to tests done at Berkeley, compilers just aren't using all those
instructions anyway.  One benchmark observed that 10 instructions (out of 360) 
accounted for 80% of all instructions executed, 21 instructions for 95% of 
executed instructions, and only 30 instructions acounted for 99% of executed 
code.  (Alexander & Wortman, 1975, on IBM System/360, using XPL language).