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From: vaughan@mcc.com (Paul Vaughan)
Newsgroups: comp.sys.mips,comp.arch
Subject: Re: Mips, Mach, test-and-set
Message-ID: <3421@cadillac.CAD.MCC.COM>
Date: 20 Oct 89 18:14:24 GMT
References: <2591@ganymede.inmos.co.uk> <6831@hubcap.clemson.edu>
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Reply-To: vaughan@mcc.com (Paul Vaughan)
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In-reply-to: mark@hubcap.clemson.edu (Mark Smotherman)


	This is a little off the topic of test-and-set, because it has
to do with multiple processor synchronization rather than multiple
process synchronization. But, . . .
	How many of you are familiar with the fetch&op circuit for
interprocessor arithmetic and synchronization developed by G.J.
Lipovski at the University of Texas?  It is a tree based circuit with
as few as 5 gates per node (bit serial) that allows a form of
combining addition (fetch&add), as well as a wide variety of
synchronization and priority operations between multiple processors.
As far as hardware support for multiple processor synchronization
goes, it is about as simple as can be implemented, but it can do a lot
of useful things.  How popular is the fetch&add hardware model for
designing parallel algorithms?


 Paul Vaughan, MCC CAD Program | ARPA: vaughan@mcc.com | Phone: [512] 338-3639
 Box 200195, Austin, TX 78720  | UUCP: ...!cs.utexas.edu!milano!cadillac!vaughan