Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!sun-barr!newstop!sun!imagen!atari!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Alliant/Intel PAX parallel computing standard
Message-ID: <23184@cup.portal.com>
Date: 19 Oct 89 19:27:24 GMT
Organization: The Portal System (TM)
Lines: 22

Alliant Computer and Intel announced a deal earlier this week, which involves
a $3 million investment in Alliant from Intel, and the transfer from
Alliant to Intel, for resale, of their parallelizing compilers.

Another key part of the deal is the establishment of the PAX (parallel
architecture extension), to become part of a multiprocessor binary standard
for i860-based machines.  Alliant has been building machines with hardware
support for loop-level parallelism, and Intel will be building this
technology into their next-generation i860 silicon.  (Intel is evasive on
whether the support will all be in the processor chip, or in support chips.)
The PAX standard seems to involve lots of levels, including the API,
the OS, the binary format, and scheduling and synchronization hardware.
Essentially no details were provided in the announcement.

Is anyone familiar with Alliant's loop-level parallelism scheme?
Intel is pitching this as a major win for the i860, in that it gives them
a binary standard for parallel computing, something no other processor has.
Does anyone think this is really significant?

Michael Slater, Microprocessor Report   mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto CA 94306
415/494-2677   fax: 415/494-3718