Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!amdcad!sun!chiba!khb
From: khb%chiba@Sun.COM (Keith Bierman - SPD Advanced Languages)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <126596@sun.Eng.Sun.COM>
Date: 20 Oct 89 16:55:05 GMT
References: <1989Oct19.155752.13028@mentor.com>
Sender: news@sun.Eng.Sun.COM
Reply-To: khb@sun.UUCP (Keith Bierman - SPD Advanced Languages)
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Organization: Sun Microsystems, Mountain View
Lines: 17

In article <1989Oct19.155752.13028@mentor.com> geraldp@mentor.com (Gerald Page) writes:

>
>2.  All instructions (operations) consume a single processor cycle with the
>    possible exceptions of LOAD and STORE.

I know of NO machine which performs singe floating point OPS in 1
cycle (some machines can achieve 1 fop/cycle when the pipes can be
kept full). Are there counterexamples, or is #2 simply at variance
with reality ?
Keith H. Bierman    |*My thoughts are my own. !! kbierman@sun.com
It's Not My Fault   |	MTS --Only my work belongs to Sun* 
I Voted for Bill &  | Advanced Languages/Floating Point Group            
Opus                | "When the going gets Weird .. the Weird turn PRO"

"There is NO defense against the attack of the KILLER MICROS!"
			Eugene Brooks