Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!dg!chris
From: chris@dg.dg.com (Chris Moriondo)
Newsgroups: comp.arch
Subject: Re: ATTACK OF KILLER MICROS
Message-ID: <223@dg.dg.com>
Date: 20 Oct 89 21:24:54 GMT
References: <35825@lll-winken.LLNL.GOV> <1081@m3.mfci.UUCP> <35896@lll-winken.LLNL.GOV> <33798@ames.arc.nasa.gov> <35977@lll-winken.LLNL.GOV> <220@dg.dg.com> <1989Oct19.172050.20818@ux1.cso.uiuc.edu>
Reply-To: chris@dg.dg.com (Chris Moriondo)
Organization: Data General, Westboro, MA.
Lines: 33

In article <1989Oct19.172050.20818@ux1.cso.uiuc.edu> hsu@uicsrd.csrd.uiuc.edu (William Tsun-Yuk Hsu) writes:
>In article <220@dg.dg.com> chris@dg.dg.com (Chris Moriondo) writes:
>>
>>The only really scalable interconnect schemes of which I am aware are
>>multistage interconnects which grow (N log N) as you linearly increase the
>>numbers of processors and memories...
>>
>>While message passing multicomputers maximize programmer effort in the sense
>>that they don't lend themselves to "dusty deck" programs, they have the
>>advantage that the interconnect costs scale linearly with the size machine.
>
>Ummm, message passing does not necessarily mean a single-stage 
>interconnect. Also, most commercial message passing systems these
>days are hypercubes...

Too right.  I confess I was thinking more along the lines of the current
crop of fine-grained mesh-connected message-passing multicomputers that are
being worked on at CALTECH (Mosaic) and MIT (the Jelly-bean machine and
the Apiary.)  At least with machines of this ilk you only pay message latency
proportional to how far you are communicating, rather than paying on every
(global) memory reference with the shared-memory approach.  Some of the
hot-spot contention results indicate that the cost of accessing memory as
seen by a processor might bear little relationship to its own referencing
behavior.

>...and it's oversimplifying to claim that the
>cost of the hypercube interconnect scales linearly with system size.
>Remember that there are O(logN) ports per processor.

With hypercubes, what concerns me more than the scaling of the number of
ports is the scaling of the length of the longest wires, and the scaling of
the number of wires across the midpoint of the machine.  (Unless of course
you can figure out a way to wire your hypercube in hyperspace...  :-)