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From: frazier@oahu.cs.ucla.edu (Greg Frazier)
Newsgroups: comp.arch
Subject: Re: ERISC???
Message-ID: <28357@shemp.CS.UCLA.EDU>
Date: 21 Oct 89 06:52:01 GMT
References: <1989Oct19.155752.13028@mentor.com> <126596@sun.Eng.Sun.COM>
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Reply-To: frazier@oahu.UUCP (Greg Frazier)
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Organization: UCLA Computer Science Department
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In article <126596@sun.Eng.Sun.COM> khb@sun.UUCP (Keith Bierman - SPD Advanced Languages) writes:
>In article <1989Oct19.155752.13028@mentor.com> geraldp@mentor.com (Gerald Page) writes:
>>2.  All instructions (operations) consume a single processor cycle with the
>>    possible exceptions of LOAD and STORE.
>I know of NO machine which performs singe floating point OPS in 1
>cycle (some machines can achieve 1 fop/cycle when the pipes can be
>kept full). Are there counterexamples, or is #2 simply at variance
>with reality ?

First of all, yes, there are machines with single cycle (25 ns)
FP adders and multipliers:

%T An Integrated Floating Point Vector Processor for
DSP and Scientific Computing
%A D. Spaderna
%A P. Green
%A K. Tam
%A T. Datta
%A M. Kumar
%J IEEE International Conference on Computer Design:
VLSI in Computers and Processors
%D October, 1989
%P 8-13
%C Cambridge, MA

Second, the RISC concept specifically addressed integer
engines and pulling memory closer to the processor.  The
six "characteristics of a RISC processor" previously
mentioned are specifically the goals/features of the
Berkeley RISC (which came first, the goal or the feature? :-),
and second, a way to establish a category of processors.
At the time RISC was being conceived, both at IBM and
at Berkely, nobody was putting FP on the same chip as
the processor.  FP operations were "remote calls", if
you will.  Heck, caches weren't even on chip.  The field
of VLSI architectures is changing too fast to get religious
about how to make a fast processor.  Of course, the issue
here isn't whether machines like the 860 and 960, which
implement multi-cycle FP instructions, are fast - they
are - the issue is whether or not they are RISC.  And the
answer is... who cares?  The people who made RISC famous -
Patterson et. al. - clearly stated a set of characteristics
which they said defined a RISC processor.  Coincidentally (?),
the RISC I and RISC II processors displayed these characteristics.
Now, if you want to re-define RISC to include machines like
the 860, that's fine; I don't think anybody's patented the
term, and I don't even know who used it first.  But don't
get upset when somebody tells you that so-and-so processor
is/isn't a RISC - just keep in mind that the taxonomy is
completely artificial, and all that really matters is how
fast it goes.

Greg Frazier
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Greg Frazier	frazier@CS.UCLA.EDU	!{ucbvax,rutgers}!ucla-cs!frazier