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From: vestal@SRC.Honeywell.COM (Steve Vestal)
Newsgroups: comp.lsi
Subject: On-Line Detection
Message-ID: <35374@srcsip.UUCP>
Date: 18 Oct 89 15:24:08 GMT
Sender: news@src.honeywell.COM
Lines: 14

I'm trying to learn a little more about what I've seen called on-line or
concurrent fault/error detection; e.g., the use of parity, ECC, M of N voting,
etc. within circuits to detect faults/errors.  I'm more interested in
detection than masking/correction, and I'm particularly interested in
implementation complexity/overhead and modeling issues like fault latency,
coverage, etc.

I would greatly appreciate it if someone would email me some references,
perhaps the name of a favorite text, that would give me an introduction
to these issues.

Steve Vestal
Mail: Honeywell S&RC MN65-2100, 3660 Technology Drive, Minneapolis MN 55418 
Phone: (612) 782-7049                    Internet: vestal@src.honeywell.com