Path: utzoo!attcan!telly!lethe!torsqnt!jarvis.csri.toronto.edu!mailrus!iuvax!cica!gatech!emory!auc!rar
From: rar@auc.UUCP (Rodney Ricks)
Newsgroups: comp.sys.amiga
Subject: Re: Fix that baby! (RAM Board clarifications)
Summary: A 68000 bus cycle is four cpu clock cycles, isn't it?
Keywords: memory bus
Message-ID: <32285@auc.UUCP>
Date: 22 Sep 89 13:53:47 GMT
References: <2367@hub.UUCP>
Reply-To: rar@auc.UUCP (Rodney Ricks)
Distribution: na
Organization: Atlanta University Center, Atlanta, Ga.
Lines: 31

In article <2367@hub.UUCP> dougp@voodoo.ucsb.edu writes:
>-Message-Text-Follows-
>In article <7966@cbmvax.UUCP>, daveh@cbmvax.UUCP (Dave Haynie) writes...
>>has a cycle time of 270ns or better.  The _minimum_ memory cycle time on 
>>the Amiga bus is 560ns.  Clearly, some margin exists for a good design using
>                  ^^^^^ Is this always true? My understanding is that
>the 68000 only needs to access ram every other cycle which would
>explain the timing (well almost, 1/7.14Mhz = 140ns, *2=280ns).

I'm no hardware expert, but from my understanding, doesn't the 68000 have
four CPU clock cycles for every memory bus cycle?  If so, that would change
your timing calculation to be...

1 / 7.14 Mhz = 140ns, 140ns * 4 = 560ns

>But other devices hanging on the bus, say a hard disk with DMA, or
>even the 2620 might be able to access the bus every cycle.

Maybe the bus was designed to run only as fast as the 7.14 Mhz 68000
can access it.

>>Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
>>   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
>
>Douglas Peale

-- 
"We may have come over here in different ships,
 but we're all in the same boat now."   --   Jesse Jackson

Rodney Ricks,   Morehouse Software Group