Path: utzoo!attcan!uunet!ginosko!cs.utexas.edu!sun-barr!newstop!sun!shukra!ram
From: ram@shukra.Sun.COM (Renu Raman)
Newsgroups: comp.arch
Subject: Re: Gate delays in fast computers
Message-ID: <126676@sun.Eng.Sun.COM>
Date: 22 Oct 89 09:08:51 GMT
References: <29862@obiwan.mips.COM>
Sender: news@sun.Eng.Sun.COM
Reply-To: ram@sun.UUCP (Renu Raman)
Organization: Sun Microsystems, Mountain View
Lines: 19

In article <29862@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>
> 

Talks about gate-delay/cycle i.e. average (or maybe max) no. gates between
latches.

>Cray-3.  A pair of listings leaped off the screen and really astonished me:
>
>	Instruction issue rate:			1 new instruction per cycle
>	# of gate delays per clock cycle:	6 gate delays per cycle
>
> -- Mark Johnson	

   Cray-1 had 8.

   renu raman

   email: ram@sun.com