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From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Gate delays in fast computers
Message-ID: <6640@pt.cs.cmu.edu>
Date: 23 Oct 89 15:57:02 GMT
References: <29862@obiwan.mips.COM>
Organization: Carnegie-Mellon University, CS/RI
Lines: 13

In article <29862@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>For a "well designed" computer, how many gate delays are there in one
>clock cycle??  That is, what's the ratio [(cycle time)/(gate delay)]?

Cray 1S		8
Cray 2		4	
Cray 3		6

The Cray-2 gets pipe results every clock, but takes two clocks per
instruction issue. So, the low ratio hurt the scalar performance.
This may represent a true lower bound.
-- 
Don		D.C.Lindsay 	Carnegie Mellon Computer Science