Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!rpi!plato.rdrc.rpi.edu!kyriazis
From: kyriazis@plato.rdrc.rpi.edu (George Kyriazis)
Newsgroups: comp.arch
Subject: Re: Gate delays in fast computers
Message-ID: <1989Oct23.224916.11282@rpi.edu>
Date: 23 Oct 89 22:49:16 GMT
References: <29862@obiwan.mips.COM> <126676@sun.Eng.Sun.COM>
Reply-To: kyriazis@plato.rdrc.rpi.edu.UUCP (George Kyriazis)
Organization: Rensselaer Polytechnic Institute, Troy NY
Lines: 25

In article <126676@sun.Eng.Sun.COM> ram@sun.UUCP (Renu Raman) writes:
>
>>Cray-3.  A pair of listings leaped off the screen and really astonished me:
>>
>>	Instruction issue rate:			1 new instruction per cycle
>>	# of gate delays per clock cycle:	6 gate delays per cycle
>>
>> -- Mark Johnson	
>
>   Cray-1 had 8.
>
>   renu raman
>

Remember also that the Crays are pipelined machines, so this is 
probably not the total number of gates delays that each instruction goes
through, but the number of gates delays each instruction goes through
at EACH clock cycle.  



  George Kyriazis
  kyriazis@turing.cs.rpi.edu
  kyriazis@rdrc.rpi.edu
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