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From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Gate delays in fast computers
Message-ID: <34291@ames.arc.nasa.gov>
Date: 23 Oct 89 19:47:23 GMT
References: <29862@obiwan.mips.COM>
Sender: yee@ames.arc.nasa.gov
Organization: NASA - Ames Research Center
Lines: 21

In article <29862@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:

>Pedagogical question: is there a "correct value" for gate delays per clock
>cycle that represents a good tradeoff, empirically determined over the
>last 30 years, that's best in fast machines?

Waser and Flynn's "Arithmetic.." has a section on this.  Segmented FPU's
such as carry-look-ahead adders and multipliers using Booth's encoder w/ Wallace
tree, which are segmented at 4-delay intervals, are "optimal" by their criteria,
but I think the rules may change in micros.  You see a lot of machines
from the mid 60's to the mid 80's use segmented functional units with various
design choices that look familiar from reading the book.  These days, gate 
delay is not the single dominating factor that it once was, so I don't
know if there is a simple-minded recipe available.  MIPSCo got excellent
results on the R3010, but I don't know what approach was used.  Anyway, some
of the basics are in Waser and Flynn.  See Ch. 6.

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117