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From: gillies@m.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: 1000000x1000000 Matrix (was: li
Message-ID: <3300080@m.cs.uiuc.edu>
Date: 25 Oct 89 16:27:25 GMT
References: <36621@lll-winken.LLNL.GOV>
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Nf-ID: #R:lll-winken.LLNL.GOV:36621:m.cs.uiuc.edu:3300080:000:669
Nf-From: m.cs.uiuc.edu!gillies    Oct 24 23:48:00 1989


Re: KILLER MICROS

At some point I heard that MIPS pulled out just about every stopper to
speed up the floating point speed of the R2000/R3000.  In other words,
they hardwired all the FPU ops, and provided 32 or 64-bit circuitry
wherever it was needed, and used all the optimal designs (like carry
lookahead and wallace trees -- please excuse my ignorance of
arithmetic circuitry) in their arithmetic unit?

So now they just wait for device technology and heavy pipelining to
speed up their chip?  Couldn't Crays make a small comeback by
exploiting their 1's complement arithmetic, which is supposed to be an
inherently faster number system for digital implementation?